1. Field of the Invention
The present invention relates to a thermal type recording apparatus, and more particularly to the thermal type recording apparatus which operates to do recording at halftone density by changing an energizing time of a thermal head.
2. Description of the Related Art
A thermal head section of the conventional sublimating type printer for enabling halftone recording is illustrated in FIG. 8. The thermal head section is arranged to have a thermal head or a thermal element (referred to as "head") 81, a platen 83, an image-receiving paper 82 and an ink ribbon 86. The image-receiving paper 82 and the ink ribbon 86 are laid between the head 81 and the platen 83. The ink ribbon 86 is heated by the head 81 so that the ink on the ink ribbon 86 is transferred onto the image-receiving paper 82. The ink ribbon 86 is fed or wound around two rollers 84 and 85 along the progress of printing.
FIG. 9 shows a driving circuit of the head 81. The head 81 provides n heads (n is an integer). Resistors R1 to Rn stand for the heads. Each one end of the resistors R1 to Rn is commonly connected to a power supply VTH and the other ends are respectively connected to the collectors of NPN transistors TR1 to TRn. The emitters of the transistors TR1 to TRn are connected on the ground GND. The bases of the transistors TR1 to TRn are respectively connected to the outputs of the AND circuits GT1 to GTn.
A strobe signal STRB is fed to one inputs of the AND circuits GT1 to GTn. The other inputs of the AND circuits are connected to an output Q of flip-flop circuits (referred to as "FF circuit") FF1 to FFn. And, an active load pulse LOAD is fed to the set inputs S of the FF circuits FF1 to FFn. The reset inputs are connected to the outputs of L active circuits INV1 to INVn.
If, therefore, the L active load pulse LOAD is input and the FF circuits FF1 to FFn are set so that those outputs Q are made to be at high level when the strobe signal STRB is at high level, the outputs of the AND circuits CT1 to GTn are made at high level. The transistors TR1 to TRn are turned on so that current may flow through the resistors R1 to Rn, thereby heating the thermal elements. On the other hand, if the inverting circuits INV1 to INVn supplies L-level outputs, the corresponding FF circuits FF1 to FFn are reset so as that those outputs Q are made at L level. Hence, the energizing of the corresponding transistors TR1 to TRn is interrupted so that heating of the corresponding resistors R1 to Rn may be stopped.
Counters CNT1 to CNTn denote synchronous up counters which may load four-bit initial numerical values. This counter is counted up at a leading edge of a clock TPW. When the asynchronous L active load pulse LOAD is made at L level, the values fed to the inputs A to D are read and are output at the output QA to QD. After the count value of the counter reaches zero, the output MAX is made at H level at the leading edge of the fifteenth clock TPW and then is returned to L level at the leading edge of the next clock. Those counters serve to feed H-level signals to the inverting circuits INV1 to INVn on a predetermined timing, respectively, for controlling the energizing times of the resistors R1 to Rn. The inputs A to D of the counters are connected to the outputs QA to QD of the latch circuits L1 to Ln. Each output MAX is connected to the inputs of the inverting circuits INV1 to INVn.
Data D1 to D4 are fed to the inputs 1D to 4D of the latch circuit L1, the outputs QA to QD of which are connected to the inputs 1D to 4D of the latch circuit L2. Likewise, with respect to the latch circuits L3 to Ln-1, the input of each latch is connected to the outputs of the latch circuits having one smaller number. The output of each latch is connected to an input of each latch circuit having one larger number. The outputs QA to QD of the latch circuit Ln are respectively connected to the inputs A to D of the counter CNTn. A latch pulse TD is fed to the clock inputs T of the latch circuits L1 to Ln.
The operation of the driving circuit arranged as above will be described as referring to a timing chart of FIG. 10. In this embodiment, the number n of heads is 256 and the strobe signal STRB is constantly kept at H level. Further, the description will be made as taking an example of controlling the energizing of the resistor R1.
On the timing when each scan is started, an L-level load pulse LOAD is input so as to set the FF circuit FF1. Hence, the output of the AND circuit GT1 is made at H level, the transistor TR1 is switched on and the energizing of the resistance R1 is started.
On the other hand, as a latch pulse TD, the same number, 256, of pulses as the elements for each scan are input and data D1 to D4 are fed in synchronous to each latch pulse TD. For example, when starting M-th scan (M scan), an L-level load pulse LOAD is input. If a first latch pulse TD is input on the timing, the data D1 to D4 being fed are latched by a latch circuit L1 and are fed to the counter CNT1. And, since the L-active load pulse LOAD is at L level, the counter CNT1 operates to read data from the latch circuit L1 and use it as an initial value for calculation. Then, when the clock TPW is input and the count value reaches 15, the counter CNT1 outputs a H-level signal at the output MAX.
For example, if the first given data D1 to D4 are 0, 0, 1 and 1, the outputs QA to QD of the latch circuit L1 are made to be 0, 0, 1 and 1 and the initial count value of the counter CNT1 reaches 12. Hence, when a third clock TPW is input, the output MAX is made at H level. Hence, assuming that one period of the clock TPW is t0, after feeding the L-level load pulse LOAD, the output Q of the FF circuit FF1 is maintained for a period of 3.multidot.t0. Then, when the output MAX reaches H level, the FF circuit FF1 is reset so that the output Q may reach L level. That is, if 0, 0, 1 and 1 are given at data D1 to D4, the resistor R1 is energized for a period of 3.multidot.t0.
Next, it is assumed that at the (M+1) th scan, 0, 0, 0, 1 are given as data D1 to D4. In this case, the counter CNT1 starts to count with an initial value of 8. At a time when a seventh clock TPW is input, the output MAX is at H level. Hence, the resistor R1 is energized for a period of 7.multidot.t0.
It is assumed that at the (M+2)th scan, 1, 1, 0, 0 are given at data D1 to D4. In this case, the counter CNT1 starts to count with an initial value of 3. When the twelve clock TPW is input, the output MAX is made at H level. Hence, the resistor R1 is energized for a period of 12.multidot.t0.
In general, assuming that the values of the data D1 to D4 are K, the resistor R1 is kept energized for a period of (2.sup.4 -1-K).multidot.t0.
That is, by changing the values of the data D1 to D4, it is possible to change the energizing time of the thermal elements and perform halftone recording more easily.
In such a conventional printer, however, as shown by a graph of FIG. 15, the printing density (2) is not proportional to the energizing time. In particular, if the energizing time is 1.multidot.t0, 2.multidot.t0, and 3.multidot.t0, no first tone to third tone printing is performed. In addition, the maximum density is not printed satisfactorily.
To solve these problems, for enhancing the voltage applied to the head, the leading of the thermal head temperature (1) is made acute as shown in FIG. 18, thereby expanding the printing range at low tone. However, there may take place a problem that the printing density (2) is saturated at high tone. Further, this problem holds true to the case that the head is affected by an ambient temperature or the temperature of the head is changed.